1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and its writing method. In particular, the present invention relates to a NOR type flash memory and its writing method.
2. Related Art
In general, the NOR type flash memory has a plurality of memory cells arranged in a matrix form. Each memory cell includes a source region and a drain region formed in a semiconductor substrate, a gate insulation film formed on the semiconductor substrate to serve as a channel region between the source region and the drain region, a floating gate formed on the gate insulation film, an inter-electrode insulation film formed on the floating gate, and a control gate formed on the inter-electrode insulation film.
A memory cell in a column shares the source region or drain region with adjacent memory cells in the same column. Drain regions of memory cells in the same column are connected to a common bit line in parallel via bit line contacts. Control gates respectively of memory cells in the same row are connected to a common word line.
In the NOR type flash memory having such a configuration, threshold adjustment (writing) of each memory cell is conducted by injecting channel hot electrons, which are generated by applying predetermined voltages to the control gate and the drain region and connecting the source region and the semiconductor substrate to the ground potential, into the floating gate. In the NOR type flash memory, therefore, it is important to the writing efficiency to generate channel hot electrons by the drain voltage. As one of techniques for increasing the writing efficiency, it is conducted to increase the hot electrons by forming a bipolar transistor in the drain region (see, for example, Liyang Pan, Jun Zhu, Zhihong Liu, Ying Zeng, and Jianzhao Liu, “Novel Self-Convergent Programming Method Using Source-Induced Band-to-Band Hot Electron Injection,” IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 11, P. 652, NOVEMBER 2002).
In the NOR type flash memory, however, the gate electrode length is made fine in order to implement high integration. As a result, parasitic resistance such as diffusion layer resistance and contact resistance becomes large relatively. Therefore, the effective drain voltage applied to the channel region is getting lower and lower. This results in a problem that the writing efficiency is reduced.